Electronics Engineering

Electronics EngineeringGeneral AptitudeNumerical Answer (NAT)2 Marks
Q6.

In the circuit shown below, the AND gate has a propagation delay of 11 ns. The edge-triggered flip-flops have a set-up time of 22 ns, a hold-time of 00 ns, and a clock-to-Q delay of 22 ns.

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The maximum clock frequency (in MHz, rounded off to the nearest integer) such that there are no setup violations is ________.

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