Computer Science And Engineering - Computer Organization & Architecture (COA) PYQ

Q1.MCQ

Consider a memory system with $1\text{M}$ bytes of main memory and $16\text{K}$ bytes of cache memory. Assume that the processor generates $20$-bit memory address, and the cache block size is $16$ bytes. If the cache uses direct mapping, how many bits will be required to store all the $tag$ values? Assume memory is byte addressable, $1\text{K} = 2^{10}$, $1\text{M} = 2^{20}$.

Q2.MCQ

A processor has $64$ general-purpose registers and $50$ distinct instruction types. An instruction is encoded in $32$-bits. What is the maximum number of bits that can be used to store the immediate operand for the given instruction? ADD R1, 25 // R1 = R1 + 25

Q3.MCQ

Suppose a program is running on a non-pipelined single processor computer system. The computer is connected to an external device that can interrupt the processor asynchronously. The processor needs to execute the interrupt service routine (ISR) to serve this interrupt. The following steps (not necessarily in order) are taken by the processor when the interrupt arrives: (i) The processor saves the content of the program counter. (ii) The program counter is loaded with the start address of the ISR. (iii) The processor finishes the present instruction. Which ONE of the following is the CORRECT sequence of steps?

Q4.NUMERICAL

A computer has a memory hierarchy consisting of two-level cache (L1 and L2) and a main memory. If the processor needs to access data from memory, it first looks into L1 cache. If the data is not found in L1 cache, it goes to L2 cache. If it fails to get the data from L2 cache, it goes to main memory, where the data is definitely available. Hit rates and access times of various memory units are shown in the figure. The average memory access time in nanoseconds (ns) is . (rounded off to two decimal places) !image(https://uadmin.udsfgecw.tech/file/download/public/public:3f2b011b-c6e8-46ee-9666-c45dadc7480f.jpg)

Q5.M-MCQ

A partial data path of a processor is given in the figure, where RA, RB, and RZ are 32-bit registers. Which option(s) is/are CORRECT related to arithmetic operations using the data path as shown? image needed to be inserted here

Q6.M-MCQ

Consider two set-associative cache memory architectures: WBC, which uses the write back policy, and WTC, which uses the write through policy. Both of them use the LRU (Least Recently Used) block replacement policy. The cache memory is connected to the main memory. Which of the following statements is/are TRUE?

Q7.NUMERICAL

Consider a $512\text{ GB}$ hard disk with $32$ storage surfaces. There are $4096$ sectors per track and each sector holds $1024$ bytes of data. The number of cylinders in the hard disk is

Q8.NUMERICAL

The baseline execution time of a program on a $2\text{ GHz}$ single core machine is $100\text{ nanoseconds}$ ($ns$). The code corresponding to $90\%$ of the execution time can be fully parallelized. The overhead for using an additional core is $10\text{ ns}$ when running on a multicore system. Assume that all cores in the multicore system run their share of the parallelized code for an equal amount of time. The number of cores that minimize the execution time of the program is

Q9.NUMERICAL

A given program has $25\%$ load/store instructions. Suppose the ideal CPI (cycles per instruction) without any memory stalls is $2$. The program exhibits $2\%$ miss rate on instruction cache and $8\%$ miss rate on data cache. The miss penalty is $100$ cycles. The speedup (rounded off to two decimal places) achieved with a perfect cache (i.e., with NO data or instruction cache misses) is

Q10.NUMERICAL

A machine has a 32-bit architecture with 1-word long instructions. It has 24 registers and supports an instruction set of size 40. Each instruction has five distinct fields, namely opcode, two source register identifiers, one destination register identifier, and an immediate value. Assuming that the immediate operand is an unsigned integer, its maximum value is .